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RT9396 1 ds9396-01 april 2011 www.richtek.com ordering information note : richtek products are : rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. suitable for use in snpb or pb-free soldering processes. i 2 c interface pmic with 6-channel wled driver and 4-ldo general description the RT9396 is a power management ic (pmic) for backlighting and phone camera applications. the pmic contains a 6-channel charge pump white led driver and four low dropout linear regulators. the charge pump drives up to 6 white leds with regulated constant current for uniform intensity. each channel (led1 to led6) supports up to 25ma of current. these 6-channels can be also programmed as 4 plus 2-channels or 5 plus 1-channel with different current setting for auxiliary led application. the RT9396 maintains highest efficiency by utilizing a x1/ x1.5/ x2 fractional charge pump and low dropout current regulators. an internal 6-bit dac is used for backlight brightness control. users can easily configure up to 64 steps of led current via the i 2 c interface control. the RT9396 also comprises low noise, low dropout regulators, which provide up to 200ma of current for each of the four channels. the four ldos deliver 3% output accuracy and low dropout voltage of 200mv @ 200ma. users can easily configure ldo output voltage via the i 2 c interface control. the ldos also provide current limiting and over temperature functions. the RT9396 is available in a wqfn-24l 3x3 package. features z z z z z tri-mode (x1/x1.5/x2) charge pump z z z z z maximum 25ma x 6-channel led backlighting output current z z z z z support main/sub (4+2/5+1) led function z z z z z 64 steps programmable led current z z z z z support pwm dimming function z z z z z fade in/out via i 2 c control z z z z z 4 low dropout regulators z z z z z maximum 200ma x 4-channel ldo output current z z z z z 16-level ldo output voltage setting z z z z z i 2 c programmable independent ldo channel on/off control z z z z z over temperature protection z z z z z thin 24-lead wqfn package z z z z z rohs compliant and halogen free applications z cellular phones z pdas and smart phones pgnd c2n c1n c1p c2p ldo2 agnd vin ldoin ldo3 ldo4 scl sda pwm cf en led3 led5 vout led1 led2 led4 ldo1 led6 1 2 3 4 5 6789 11 10 17 16 15 14 13 21 20 19 24 22 23 12 18 pin configurations wqfn-24l 3x3 (col) (top view) RT9396 package type qw : wqfn-24l 3x3 (col) (w-type) lead plating system g : green (halogen free and pb free)
RT9396 2 ds9396-01 april 2011 www.richtek.com typical application circuit timing diagram marking information jp= : product code ymdnn : date code jp=ym dnn figure 1. timing diagram c2n led4 c out vin c1p c1n c2p RT9396 en vout led3 led2 led1 c fly2 1f c fly1 1f c in1 2.2f 1 5 4 7 2 4 3 2 5 2 3 2 2 2 1 2 0 1f 1 9 led5 led6 1 8 v bat wled c l1 ldo1 1 2 1f c l2 ldo2 1 1 1f agnd 6 c l3 ldo3 1 0 1f c l4 ldo4 9 1f chip enable scl 1 7 sda 1 6 i 2 c pwm 1 4 pwm ldoin c in2 2.2f 8 1 3 c f 1f cf pgnd 1 time (s) t shd = 16ms 0 main i led [1:6] 00000000 01111101 fade in/out time = 8ms/step, i led [1~6] = 62/64 x 25ma main bl current level internal pwmen reg. i 2 c reg. addr. pwm pin 010 led<1:6> on/off pwm dimming t hi > 0.5s 0.5s < t lo < 500s pwm control backlight 00000000 i 2 c reg. data 01011111 6ch pwm mode note: pwm signal rise after internal pwmen is enabled i led [1~6] current = 62/64 x 25ma x pwm duty fade in time
RT9396 3 ds9396-01 april 2011 www.richtek.com figure 2. control sequences of ldo setting and led dimming c7 c6 c5 c4 c3 c2 c1 c0 0 x x x x x 0 1 0 b4 b3 b2 b1 b0 64-step current setting channel on/off ? i 2 c writing cycles of backlighting i (led1~6) stop start led6 led5 led4 backlight address ? i 2 c writing cycles of ldox 16-step voltage setting 0 0 1 b4 b3 b2 b1 b0 0 0 0 0 c3 c2 c1 c0 start stop 1 0 1 0 1 0 0 0 channel selection ldo address ldo1 ldo2 ldo3 ldo4 led1~3 blon fade in/out setting 1 0 1 0 1 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0 0 x x x x x 0 1 1 0 b3 b2 b1 b0 main 64-step current setting channel on/off ? i 2 c writing cycles of backlighting ii (main: led1~5, sub: led6) stop start led5 led4 backlight address led1~3 main on main fade in/out setting 1 0 1 0 1 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0 0 x x x x x 1 0 0 0 b2 0 b1 b0 channel on/off ? i 2 c writing cycles of backlighting iii (main: led1~4, sub: led5~6) stop start led4 backlight address led1~3 main on fade in/out setting 1 0 1 0 1 0 0 0 main fade in/out setting: 01: every step of fade in/out = 8 ms 10: every step of fade in/out = 16 ms 11: every step of fade in/out = 32 ms pwmen c7 c6 c5 c4 c3 c2 c1 c0 0 x x x x x 0 1 1 1 0 0 0 b0 sub 64-step current setting channel on/off stop start backlight address led6 sub on sub fade in/out setting 1 0 1 0 1 0 0 0 main fade in/out setting: 01: every step of fade in/out = 8 ms 10: every step of fade in/out = 16 ms 11: every step of fade in/out = 32 ms sub fade in/out setting: 01: every step of fade in/out = 8 ms 10: every step of fade in/out = 16 ms 11: every step of fade in/out = 32 ms pwmen pwmen main fade in/out setting: 01: every step of fade in/out = 8 ms 10: every step of fade in/out = 16 ms 11: every step of fade in/out = 32 ms main 64-step current setting c7 c6 c5 c4 c3 c2 c1 c0 0 x x x x x 1 0 0 1 0 0 0 b0 channel on/off stop start backlight address led5~6 sub on fade in/out setting 1 0 1 0 1 0 0 0 sub sub fade in/out setting: 01: every step of fade in/out = 8 ms 10: every step of fade in/out = 16 ms 11: every step of fade in/out = 32 ms sub 64-step current setting on/off
RT9396 4 ds9396-01 april 2011 www.richtek.com functional pin description pin no. pin name pin function 1 pgnd charge pump ground. 2 c2n fly capacitor 2 negative connection. 3 c1n fly capacitor 1 negative connection. 4 c1p fly capacitor 1 positive connection. 5 c2p fly capacitor 2 positive connection. 6 agnd ground for ldo1 to ldo4. 7 vin charge pump power input. connect this pin to ldoin pin. 8 ldoin ldo power input. connect this pin to vin pin. 9 ldo4 ldo4 output. 10 ldo3 ldo3 output. 11 ldo2 ldo2 output. 12 ldo1 ldo1 output. 13 cf pwm filter capacitor connection. 14 pwm pwm dimming control input. 15 en chip enable (active high). 16 sda i 2 c data input. 17 scl i 2 c clock input. 18 led6 current sink for led6. 19 led5 current sink for led5. 20 led4 current sink for led4. 21 led3 current sink for led3. 22 led2 current sink for led2. 23 led1 current sink for led1. 24 vout charge pump output. connect a 1 f ceramic capacitor between vout and gnd.
RT9396 5 ds9396-01 april 2011 www.richtek.com function block diagram table 1. 16-step ldo output voltage setting c3 c2 c1 c0 ldo1 & ldo2 output voltage (v) ldo3 & ldo4 output voltage (v) 0 0 0 0 1 1.1 0 0 0 1 1.1 1.2 0 0 1 0 1.2 1.4 0 0 1 1 1.3 1.7 0 1 0 0 1.5 1.8 0 1 0 1 1.6 1.9 0 1 1 0 1.8 2 0 1 1 1 2.1 2.1 c3 c2 c1 c0 ldo1 & ldo2 output voltage (v) ldo3 & ldo4 output voltage (v) 1 0 0 0 2.5 2.2 1 0 0 1 2.6 2.3 1 0 1 0 2.7 2.4 1 0 1 1 2.8 2.5 1 1 0 0 2.9 2.8 1 1 0 1 3 2.85 1 1 1 0 3.1 3.2 1 1 1 1 3.3 3.3 vin vout c1p c2p c1n c2n gate driver mode decision 1mhz oscillator x1/x1.5/x2 charge pump current source soft start ovp led4 led5 led6 led3 led2 led1 current setting pwm dimming shutdown delay otp & current bias bandgap reference + - led ctrl. i 2 c por or gate ldo ctrl. ldoin pgnd agnd ldoin scl sda pwm cf en ldo1 to ldo4 v out x4 res divider voltage setting
RT9396 6 ds9396-01 april 2011 www.richtek.com c5 c4 c3 c2 c1 c0 wled current (ma) 0 0 0 0 0 0 0.39 0 0 0 0 0 1 0.78 0 0 0 0 1 0 1.17 0 0 0 0 1 1 1.56 0 0 0 1 0 0 1.95 0 0 0 1 0 1 2.34 0 0 0 1 1 0 2.73 0 0 0 1 1 1 3.13 0 0 1 0 0 0 3.52 0 0 1 0 0 1 3.91 0 0 1 0 1 0 4.3 0 0 1 0 1 1 4.69 0 0 1 1 0 0 5.08 0 0 1 1 0 1 5.47 0 0 1 1 1 0 5.86 0 0 1 1 1 1 6.25 0 1 0 0 0 0 6.64 0 1 0 0 0 1 7.03 0 1 0 0 1 0 7.42 0 1 0 0 1 1 7.81 0 1 0 1 0 0 8.2 0 1 0 1 0 1 8.59 0 1 0 1 1 0 8.98 0 1 0 1 1 1 9.38 0 1 1 0 0 0 9.77 0 1 1 0 0 1 10.16 0 1 1 0 1 0 10.55 0 1 1 0 1 1 10.94 0 1 1 1 0 0 11.33 0 1 1 1 0 1 11.72 0 1 1 1 1 0 12.11 0 1 1 1 1 1 12.5 c5 c4 c3 c2 c1 c0 wled current (ma) 1 0 0 0 0 0 12.89 1 0 0 0 0 1 13.28 1 0 0 0 1 1 14.06 1 0 0 1 0 0 14.45 1 0 0 1 0 1 14.84 1 0 0 1 1 0 15.23 1 0 0 1 1 1 15.63 1 0 1 0 0 0 16.02 1 0 1 0 0 1 16.41 1 0 1 0 1 0 16.8 1 0 1 0 1 1 17.19 1 0 1 1 0 0 17.58 1 0 1 1 0 1 17.97 1 0 1 1 1 0 18.36 1 0 1 1 1 1 18.75 1 1 0 0 0 0 19.14 1 1 0 0 0 1 19.53 1 1 0 0 1 0 19.92 1 1 0 0 1 1 20.31 1 1 0 1 0 0 20.7 1 1 0 1 0 1 21.09 1 1 0 1 1 0 21.48 1 1 0 1 1 1 21.88 1 1 1 0 0 0 22.27 1 1 1 0 0 1 22.66 1 1 1 0 1 0 23.05 1 1 1 0 1 1 23.44 1 1 1 1 0 0 23.83 1 1 1 1 0 1 24.22 1 1 1 1 1 0 24.61 1 1 1 1 1 1 25 table 2. 64-step wled current setting
RT9396 7 ds9396-01 april 2011 www.richtek.com electrical characteristics recommended operating conditions (note 4) z supply input voltage, v in , v ldoin ------------------------------------------------------------------------------------ 2.8v to 5v z junction temperature range ------------------------------------------------------------------------------------------ ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------------ ? 40 c to 85 c absolute maximum ratings (note 1) z supply input voltage, v in ---------------------------------------------------------------------------------------------- ? 0.3v to 6v z output voltage, v out ------------------------------------------------------------------------------------------------------------------------------- ---------------- ? 6v to 0.3v z other pins ----------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wqfn-24l 3x3 ----------------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) wqfn-24l 3x3, ja ----------------------------------------------------------------------------------------------------- 60 c/w z junction temperature --------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ----------------------------------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) --------------------------------------------------------------------------------------------- 2kv mm (machine mode) ---------------------------------------------------------------------------------------------------- 200v (v in = v ldoin = 3.6v, c in = 2.2 f, c out = 1 f, c fly1 = c fly2 = 1 f, v f = 3.5v, i ledx = 25ma, t a = 25 c, unless otherwise specification) parameter symbol test conditions min typ max unit input power supply under -voltage lockout threshold v uvlo v in rising. 1.8 2.1 2.5 v under -voltage lockout hysteresis v uvlo -- 200 -- mv quiescent of x1 mode i q_x1 x1 mode, v in = 5v, no load, ldo[1:4] off -- 1 2 ma quiescent of x2 mode i q_x2 x2 mode, v in = 3.5v, no load, ldo[1:4] off -- 3.5 5 ma shutdown current i shdn v in = 5v, v en = 0v -- 0.5 1 a charge pump wled driver backlight i ledx accuracy ? 5 0 5 % backlight current matching ? 3 0 3 % dropout voltage -- 70 -- mv charge pump oscillator frequency -- 1000 -- khz x1 mode to x1.5 mode transition voltage (v in falling) v f = 3.5v, i out = 150ma -- 3.6 3.75 v mode transition hysteresis v f = 3.5v, i out = 150ma -- 250 -- mv over voltage protection v in = 4.5v 5.2 5.5 5.8 v to be continued
RT9396 8 ds9396-01 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit ldo1 to ldo4 input voltage v in = 2.8v to 5v 2.8 -- 5 v dropout voltage v in 2.8v, i out = 200ma -- -- 200 mv output voltage range by i 2 c setting 1.1 -- 3.3 v vout accuracy i out = 1ma ? 3 3 % line regulation v in = ( v out + 0.3v) to 5v or v in > 2.5v, whichever is larger -- -- 0.2 %/v load regulation 1ma < i out < 200ma -- -- 0.6 % current limit i li m r load = 1 230 350 600 ma quiescent current i q 4-channel all turn on -- 140 200 a shutdown current i shdn -- -- 1 a thermal shutdown t sd -- 160 -- c thermal shutdown hysteresis t sd -- 20 -- c i 2 c interface en, sda,scl pull low current i en -- 5 10 a logic-high v ih 1.4 -- -- v en, sda, scl threshold voltage logic-low v il -- -- 0.4 v sda output low voltage v cl -- -- 0.4 v scl clock frequency f scl -- -- 400 khz scl clock low period t low 1.3 -- -- s scl clock high period t high 0.6 -- -- s hold time start condition t hd_str 0.6 -- -- s setup time for repeat start t su_str 0.6 -- -- s sda data setup time t su_dat 100 -- -- ns sda data hold time t hd_dat 0.05 -- 0.9 s setup time for stop condition t su_sto 0.6 -- -- s bus free time between stop and start condition t buf 1.3 -- -- s pwm dimming control pwm dimming frequency 1 -- 200 khz pwm dimming high time 0.5 -- -- s pwm dimming low time 0.5 -- 500 s shutdown delay 16 -- -- ms
RT9396 9 ds9396-01 april 2011 www.richtek.com x2 mode quiescent current vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) quiesent current (ma) shutdown current vs. input voltage 0.550 0.575 0.600 0.625 0.650 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) shutdown current ( a ) typical operating characteristics x1 mode quiescent current vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.533.544.555.5 input voltage (v) quiesent current (ma) for charge pump efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) efficiency (%) v f = 3.5v, i ledx = 25ma led current vs. input voltage 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2.533.544.555.5 input voltage (v) led current (ma) v f = 3.5v led1 led2 led3 led4 led5 led6 x2 mode inrush current response c1p (2v/div) time (100 s/div) v out (1v/div) i in (500ma/div) v in = 2.8v, v f = 3.5v, i ledx = 25ma
RT9396 10 ds9396-01 april 2011 www.richtek.com ripple & spike v in (20mv/div) time (500ns/div) v out (20mv/div) v c1p (2v/div) v in = 3.35v, v f = 3.5v, i ledx = 25ma x1.5 mode inrush current response c1p (2v/div) time (100 s/div) v out (1v/div) i in (200ma/div) v in = 3v, v f = 3.5v, i ledx = 25ma
RT9396 11 ds9396-01 april 2011 www.richtek.com for ldo output voltage vs. temperature 3.28 3.29 3.30 3.31 3.32 3.33 3.34 -50-25 0 25 50 75100125 temperature (c) output voltage (v) v in = 4.3v, v ldo = 3.3v ldo2 ldo3 ldo1 ldo4 dropout voltage vs. load current 0 50 100 150 200 250 0 50 100 150 200 250 load current (ma) dropout voltage (v) ldo1 ldo3 ldo4 ldo2 power on scl (5v/div) time (25 s/div) v ldo1 (2v/div) i in (500ma/div) v in = 4.3v, v ldo1 = v ldo2 = 3.3v, i load = 200ma v ldo2 (2v/div) power on scl (5v/div) time (25 s/div) v ldo3 (2v/div) i in (500ma/div) v in = 4.3v, v ldo3 = v ldo4 = 3.3v, i load = 200ma v ldo4 (2v/div) line transient response v in (v) time (100 s/div) v ldo1 (20mv/div) 4.8 3.8 v ldo2 (20mv/div) v in = 3.8v to 4.8v v ldo1 = v ldo2 = 2.8v, i load = 200ma line transient response v in (v) time (100 s/div) v ldo3 (20mv/div) 4.8 3.8 v ldo4 (20mv/div) v in = 3.8v to 4.8v v ldo3 = v ldo4 = 2.8v, i load = 200ma
RT9396 12 ds9396-01 april 2011 www.richtek.com load transient response time (10 s/div) i ldo1 (200ma/div) v ldo1 (100mv/div) i ldo2 (200ma/div) v ldo2 (100mv/div) v in = 4.3v, v ldo1 = v ldo2 = 3.3v load transient response time (10 s/div) i ldo3 (200ma/div) v ldo3 (100mv/div) i ldo4 (200ma/div) v ldo4 (100mv/div) v in = 4.3v, v ldo3 = v ldo4 = 3.3v psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 10 100 1000 10000 100000 1000000 frequency (hz) psrr (dbm) v in = 4.3v, v ldo = 3.3v, i load = 200ma noise time (50ms/div) (0.2mv/div) v in = 4.3v, v ldo = 3.3v, no load noise time (50ms/div) (0.2mv/div) v in = 4.3v, v ldo = 3.3v, i load = 50ma
RT9396 13 ds9396-01 april 2011 www.richtek.com applications information the RT9396 is an i 2 c interface pmic with one 6-channel charge pump white led driver and four ldos. the charge pump provides 6-channel low dropout voltage current source to regulate up to 6 white leds. for high efficiency, the RT9396 implements a smart mode transition for charge pump operation. the four ldos are capable of delivering low dropout voltage of 200mv @ 200ma with 3% output accuracy. the i 2 c dimming function allows for a 64 steps led brightness control and 16 steps ldo voltage control. input uvlo an under voltage lockout (uvlo) function is provided to prevent unstable occurrences during start-up. the uvlo threshold is set at an input rising voltage of 2.1v typically with a hysteresis of 0.2v. the input operating voltage range of the RT9396 is from 2.8v to 5v. an input capacitor should be placed near the vin pin to reduce ripple voltage. it is recommended to use a ceramic 2.2 f or larger capacitance as the input capacitor. soft-start the RT9396 includes a soft-start circuit to limit the inrush current at power on and mode switching. the soft-start circuit limits the input current before the output voltage reaches a desired voltage level. mode decision the RT9396 uses a smart mode decision method to choose the working mode for maximum efficiency. the charge pump can operate at x1, x1.5 or x2 mode. the mode decision circuit senses the output voltage and led voltage to determine the optimum working mode. power sequence in order to assure normal operating condition, the input voltage and en should be active before the RT9396 receives the i 2 c signal, as shown in figure 3. the RT9396 can be shut down by pulling en low. when en is reset, the i 2 c signal also needs to be re-applied to resume normal operating condition. figure 3. the power sequence scl en sda i 2 c compatible interface figure 4 shows the timing diagram of the i2c interface. the RT9396 communicates with a host (master) using the standard i 2 c 2-wire interface. the two bus lines of scl and sda must be pulled high when the bus is not in use. internal pull-up resistors are installed. after the start condition, the i 2 c master sends 8-bits data, consisting of seven address bits and a following data direction bit (r/ w). the RT9396 address is 1010100 (54h) and is a receive- only (slave) device. the second word selects the register to which the data will be written. the third word contains data to write to the selected register. figure 2 shows the writing information for voltage of the four ldos and current of the six leds. in the second word, the sub-address of the four ldos is ? 001 ? and the sub-address of the led driver for different dimming modes are respectively ? 010 ? , ? 011 ? and ? 100 ? . for the ldo output voltage setting, bits b1 to b4 represent each ldo channel respectively where a ? 1 ? indicates selected and a ? 0 ? means not selected. the b0 bit controls on/off (1/ 0) mode for the selected ldo channel(s). then, in the third word, bits c0 to c3 control a 16-step setting of ldo1 to ldo4. the voltage values are listed in table 1. for led dimming, there are three operating modes (backlight i, backlight ii and backlight iii) to select from by writing respectively ? 010 ? , ? 011 ? and ? 100 ? into the first three bits of the second word. when backlight i is selected, all six leds have the same behavior. their 64- step dimming currents are set by bits c0 to c5, which are listed in table 2. the bits c6 and c7 determine the fade in/out time of each step as shown in figure 2. for backlight ii and backlight iii, two sets of leds, called main and sub, can work separately and turn on solely. it should be noticed that no matter which mode is selected, the b0 bit must be a ? 1 ? in order for te leds in the main set to be turned on.
RT9396 14 ds9396-01 april 2011 www.richtek.com figure 4. i 2 c communication sequence flying capacitors selection to attain better performance of the RT9396, the selection of peripherally appropriate capacitor and value is very important. these capacitors determine some parameters such as input/output ripple voltage, power efficiency and maximum supply current by charge pump. to reduce the input and output ripple effectively, low esr ceramic capacitors are recommended. for led driver applications, the input voltage ripple is more important than the output voltage ripple. the input ripple is influenced by the input capacitor, c in . increasing the input capacitance can further reduce the ripple. the flying capacitors ,c fly1 and c fly2 determine the supply current capability of the charge pump, which in turn influences the overall efficiency of the system. a lower capacitance will improve efficiency, but it will limit the led's current at low input voltage. for a 6 x 25ma load over the entire input voltage range of 2.8v to 5v, it is recommended to use a 1 f ceramic capacitor for c fly1 , c fly2 and c out . ldo capacitor selection like for any low dropout regulator, the external capacitors used for the RT9396 must be carefully selected for regulator stability and performance. a capacitor with capacitance larger than 1 f is placed close to the RT9396 supply input to reduce ripple. the value of this capacitor can be increased without limit. the input capacitor must be located at a distance of not more than 0.5 inch away from the input pin of the ic and tied to a clean analog ground. any good quality ceramic or tantalum capacitor can meet the requirement. the capacitor with larger value and lower esr (equivalent series resistance) provides better psrr power supply rejection ratio and line-transient response. the output capacitor must meet minimum requirement for both capacitance and esr in all ldo's applications. for stability consideration, a ceramic capacitor with minimum capacitance of 1 f and minimum esr of 20m is recommended for the output capacitor. for space-saving and performance consideration, the RT9396 is designed to work with ceramic capacitor of low esr. however, because of it's wide esr range tolerance, the RT9396 can work stably with output capacitor of other types as well. figure 5 shows the stable region for various load current and output capacitor conditions. large output capacitance can reduce noise and improve load transient response, stability, and psrr. the capacitor must be located at a distance not more than 0.5 inch away from the vout pin and tied to a clean analog ground. in backlight ii, the main set consists of led1 to led5 and led6 is the sub set. in backlight iii, the main set consists of led1 to led4, while the sub set comprises of led5 and led6. the RT9396 has another dimming function called pwm dimming, which can be enabled by selecting the b4 bit in backlight i, b3 bit in backlight ii, and b2 bit in backlight iii. once the function is enabled, a pwm signal is applied to the pwm pin to perform pwm dimming. the led current value is the current value set by c0 to c5 multiplied by the duty cycle. it is important to note that the pwm dimming function applies only to the main set. s = start condition w = write (sda = 0 ) r = read (sda = 1 ) ack = acknowledge p = stop condition i 2 c address sub adress data ii test mode scl sda channel selection r/w on/off b7 12345678912 b6 b2 b1 b0 3456789 12 3456789 c5 c4 c3 c2 c1 c0 0 s p 0b4 a0 a1 a2 a3 a4 a5 a6 b5 c7 c6 b3 ack ack ack b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 start stop a6 a5 a4 a3 a2 a1 a0 0 the 1st word (chip address, r/w) the 2nd word (sub address, data) the 3rd word (data)
RT9396 15 ds9396-01 april 2011 www.richtek.com figure 5. stable c out esr range region of stable c out esr vs. load current 0.001 0.01 0.1 1 10 100 0 50 100 150 200 250 300 load current (ma) region of stable c out esr ( ? ) region of stable c out esr ( ) unstable range stable range simulation verify v in = 5v c in = c out1 = c out2 = 1uf/x7r thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, rate of surrounding airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following the formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature and ja is the junction to ambient thermal resistance. for recommended operating conditions specification of the RT9396, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wqfn-24l 3x3 package, the thermal resistance ja is 60 c/w on the standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wqfn-24l 3x3 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT9396 package, the derating curve in figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w ) figure 6. derating curve for RT9396 package four- layer pcb layout considerations the RT9396 is a high-frequency switched-capacitor converter. for best performance, careful pcb layout is necessary. place all peripheral components as close as possible to the ic. place c in1 , c in2 , c out , c l1 , c l2 , c l3 , c l4 , c fly1 , and c fly2 near to vin, ldoin, vout, ldo1, ldo2, ldo3, ldo4, c1p, c1n, c2p, c2n, and gnd pin respectively. a short connection is highly recommended. the following guidelines should be strictly followed when designing a pcb layout for the RT9396. the exposed gnd pad must be soldered to a large ground plane for heat sinking and noise prevention. the through-hole vias located at the exposed pad is connected to the ground plane of internal layer. vin traces should be wide enough to minimize inductance and handle high currents. the trace running from the battery to the ic should be placed carefully and shielded strictly. input and output capacitors must be placed close to the ic. the connection between pins and capacitor pads should be copper traces without any through-hole via connection. the flying capacitors must be placed close to the ic. the traces running from the pins to the capacitor pads should be as wide as possible. long traces will also produce large noise radiation caused by the large dv/dt on these pins. short trace is recommended.
RT9396 16 ds9396-01 april 2011 www.richtek.com battery gnd gnd pgnd c2n c1n c1p c2p ldo2 agnd vin ldoin ldo3 ldo4 scl sda pwm cf en led3 led5 vout led1 led2 led4 ldo1 led6 1 2 3 4 5 6789 11 10 17 16 15 14 13 21 20 19 24 22 23 12 18 gnd gnd vin traces should be wide enough. output capacitor must be placed between gnd and vout to reduce noise coupling from charge pump to leds. input capacitors must be placed close to the ic. the flying capacitors must be placed close to the ic. figure 7. pcb layout guide all the traces of leds and vin running from pins to lcm module should be shielded and isolated by the ground plane. the shielding prevents the interference of high frequency noise coupled from the charge pump.
RT9396 17 ds9396-01 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.900 3.100 0.114 0.122 e 2.900 3.100 0.114 0.122 e 0.400 0.016 l 0.350 0.450 0.014 0.018 l1 0.950 1.050 0.037 0.041 w-type 24l qfn 3x3 (col) package

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